This article presents an exercise on the use of Parallelware Analyzer to parallelize a simplified implementation of the LULESH benchmark using the OpenMP Common Core. It consists of the 16 most widely used constructs of OpenMP, the de facto standard for writing multithreaded code to take advantage of shared memory platforms. Parallelware Analyzer facilitates using […]
OpenMP
Parallelware Analyzer and the OpenMP Common Core: an exercise with PI
This article presents an exercise on the use of Parallelware Analyzer to parallelize an implementation of the computation of the PI number using the OpenMP Common Core. It consists of the 16 most widely used constructs of OpenMP, the de facto standard for writing multithreaded code to take advantage of shared memory platforms. Parallelware Analyzer […]
Is your algorithm running at peak performance? The roofline model
There are worlds where performance matters. For example HPC world: faster software means less wait time for the scientists. Embedded world: faster software means we can use cheaper silicon to build our product. Game world: faster software means that our game will run on slower CPUs, thus making our game more interesting to people with […]
Case Study: How we made the Canny edge detector run faster? (part 2)
In the previous post we talked about the performance improvement we obtained for the Canny edge detection algorithm. Most of the changes we did there were focused on hot loops: making memory accesses sequential and making the loops longer, which in turn allowed the compiler to autovectorize them. This made our program run significantly faster […]
Fixing defects in parallel code: an OpenMP example
Parallelware Analyzer provides a set of tools covering the most challenging steps of your parallel development workflow. You can start a trial to get access to the Paralleware Analyzer for free. In this post, we present the pwcheck tool which provides a static code analyzer to ensure that your code is defect-free and compliant with […]
Appentra’s Parallelware Trainer at NERSC Workshop
The National Energy Research Scientific Computing Center (NERSC) will host on October 17th, 2019 a one-day training event on using Appentra’s Parallelware Trainer tool to learn how to use OpenMP and OpenACC directives to develop code for Graphical Processing Units (GPUs). The objective is to improve the learning experience of NERSC users to program the […]
Parallelizing a shallow-water flow model with variable pressure
Executive Summary A team from the University of Malaga, Spain, attended the second Appentra-led hackathon, CESGAHACK-18 and made use of Appentra’s unique parallelization methodology to parallelize their shallow-water model that models salinity concentrations and temperature to understand natural flows. The model uses a computational approach that is faster than the direct simulation of flows using […]
InsideHPC | Parallware: LLVM-Based Tool for Guided Parallelization with OpenMP
Appentra will be present at OpenMPCon with a success case: The NAS Parallel Benchmark EP
The OpenMP Architecture Review Board (ARB) have announced the full line-up of world-class keynote speakers, technical presentations, tutorials and panel sessions to be hosted at the inaugural OpenMPCon Developer Conference, which will be held in Aachen, Germany, 28-30 September, 2015. ” The strength of this year’s program looks set to establish OpenMPCon as the single most important […]
Latest best practices in parallel programming in C with OpenMP (part 2)
In the second article of the series on latest best practices in parallel programming in C with the OpenMP standard, we focus our attention on source code rewriting rules that more clearly exhibit the parallelism available in the sequential source code. The idea is simple: match the programming pattern in your source code and rewrite […]