The Parallelware Technology

The use of multiple cores is now ubiquitous. From the fastest supercomputers in the world to mobile phones, multi-core hardware is now available for everyone to use. We are also increasingly seeing the use of accelerators to provide additional computational power. However, the difficulty comes in utilizing the hardware that is available. Parallel programming is hard. In an ideal world, writing software that scales to many cores and accelerators should be as easy as writing sequential code. Unfortunately this is not the case, limiting the number of applications that can maximise their use of HPC and parallel computing. If we can use HPC we reduce the time to solution and enable the use of larger computations that would be impossible with one thread on one CPU. However, the reality is that a developer needs to analyze the existing software, identify areas for parallelism and then implement the parallelism manually. This is a very complex, time-consuming task. At Appentra our mission is to change this! The core Parallelware Technology is built to help you identify and then implement correct, optimal parallelism into your code, bridging the gap between applications developed by programmers and the hardware. Fig. 1. An extension of the parallel bridge of Berkeley’s view of the parallel computing landscape. The new tower “Code” that is inserted between Applications and parallel Hardware highlights how real code sits between applications and the hardware, and that spanning the large parallelization gap can be facilitated Parallelware.